Power and Cost Issues Necessitate Rethinking Digital Design. to Reduce Design Costs, We Need to Stop Building Chip Instances, and Start Making Chip Generators Instead. Domain-specific Chip Generators Are Templates That Codify Designer Knowledge and Design

......Over the past two decades, chip designers have leveraged technology scaling and rising power budgets to rapidly scale performance, but we can no longer follow this path. Today, most chips are power limited, and changes to technology scaling beyond 90 nm have severely compromised our ability to keep power in check. Consequently, almost all systems designed today, from high-performance servers to wireless sensors, are becoming energy constrained. Years of research have taught us that the best—and perhaps only—way to save energy is to cut waste. Thus, clock and power gating have become common techniques to reduce direct energy waste in unused circuits. But power is also wasted indirectly when we waste performance. Higher performance requirements necessitate higher-energy operations, so removing performance waste reduces energy per operation. Using multiple simpler units rather than a single aggressive one, therefore, saves energy when processing parallel tasks. At the system level, this observation is driving the recent push for parallel computing. Looking forward, the best tool in our power-saving arsenal is customization, because the most effective way to reduce waste is to find a solution that accomplishes the same task with less work. By tailoring hardware to a specific application, customization not only results in energy savings by requiring less work but also improves performance, allowing an even greater reduction of the required energy. As a result, applicationspecific integrated circuits (ASICs) are often orders of magnitude more energy efficient than CPUs for a given application. However, despite the clear energyefficiency advantage of ASICs, the number of new ASICs built today is not skyrocketing, but decreasing. The reason is simple: nonrecurring engineering (NRE) costs for ASIC design have become extremely expensive, and very few applications have markets big enough to justify such costs. This uneasy [3B2-14] mmi2010060009.3d 10/12/010 12:22 Page 9